1. Field of the Invention
The present invention relates generally to the field of lithography processing. More particularly, the present invention relates to the field of lithography mask layout design and verification.
2. Description of Related Art
The layout of a lithography mask set for use in manufacturing integrated circuits (ICs), for example, may be designed by processing a layout defining a target pattern to be printed using the mask set to help compensate for lithography distortions and/or to help reduce the size of features. Designing a mask layout in this manner may therefore help increase IC yield and/or help increase performance and reduce power consumption.
The layout defining the target pattern may be processed, for example, to introduce phase-shifting mask (PSM) regions in the mask layout to help define features with dimensions less than the wavelength of the radiation to be directed through the mask set in printing the mask layout. The layout defining the target pattern may also be processed, for example, to perform optical proximity correction (OPC) to compensate for nonlinear distortions caused by optical diffraction and resist process effects, for example. Performing OPC therefore helps produce a mask layout that will print a pattern that more accurately matches the target pattern. Examples of tools that enable the processing of layouts in this manner include iN-Phase® and iN-Tandem™, both of which are developed by Numerical Technologies, Inc. of San Jose, Calif.
The resulting mask layout may be verified by performing design rule checking (DRC) to identify minimum line and minimum space violation errors. The resulting mask layout may also be verified by simulating a print of the mask layout for comparison against the layout defining the target pattern and identifying any errors, such as out-of-tolerance regions for example, for correction. One example of a tool that enables the verification of mask layouts in this manner is SiVL® which is also developed by Numerical Technologies, Inc.
Errors are corrected by reprocessing the entire mask layout under a different set of parameters. The reprocessed mask layout may then be again verified to identify whether the errors have been corrected or whether any new errors have been generated. Reprocessing and verification iteratively continue in this manner until the mask layout does not have any errors. Errors in a mask layout may also be manually viewed and corrected.
Because the amount of data defining a mask layout rapidly grows in size as the mask layout is processed, the time to process and verify a mask layout over multiple iterations is relatively long. The time to open a file containing such a large amount of data for manual review and error correction is also relatively long. Opening such a large data file can also destabilize an operating system and possibly cause a software crash.